Semiconductor Dies; In General
Improved methods for miniaturization of semiconductor devices have permitted the integration of millions of transistor circuit elements onto a single silicone embodiment thereof. Such a circuit is typically referred to as an integrated circuit chip or semiconductor die.
Semiconductor dies are created from a silicon wafer through the employment of various etching, doping and depositing steps that are well known in the art. Ultimately, the semiconductor die may be packaged by encapsulating the semiconductor die to form an "integrated circuit package" having a variety of pin-out or mounting and interconnection schemes. More sophisticated integrated circuit packages have been developed for very large scale integration ("VLSI") semiconductor dies. Such integrated circuit packages can accommodate the increased number of external connections required with an electronic system.
PGA and BGA Packaging
VLSI integrated circuit packages having high connection capacity are, for example, pin grid array ("PGA") and ball grid array ("BGA") type packages. Both PGA and BGA type packages, including adaptations thereof for surface mount and hybrid applications, employ one or more printed wiring boards (hereinafter referred to as "PWBs"). Such PWBs consist of, for example, polyimide, glass reinforced epoxy, ceramics, or other materials known to those skilled in the art of fabricating VLSI integrated circuit packages.
The PGA and BGA type packages differ mainly in that PGA type packages utilize conductive pins that may be either soldered to a system printed circuit board or inserted into a matching socket which is already soldered to the system printed circuit board. In contrast, BGA packages utilize "solder balls" instead of conductive pins. The solder balls of a BGA package reflow to connection points on a system printed circuit board when heated to a certain temperature, thereby electrically connecting the circuitry of the BGA integrated circuit package to external electronic circuitry.
Electrical circuits in a semiconductor die connect to bond fingers formed around the semiconductor die. Specifically, connections are made from bond pads of a semiconductor die to bond finger pads. The bond fingers are further connected, by vias and conductive leads, to either the conductive pins or conductive solder balls of a PGA type package or BGA type package, respectively. The semiconductor die is protected by encapsulation with a plastic or epoxy material. Examples of VLSI integrated circuit packages are more fully illustrated in co-pending U.S. patent application Ser. No. 07/917,894 entitled "Ball Bump Grid Array Semiconductor Packages" by Michael Rostoker, Chok J. Chia, Mark Schneider, Michael Steidl, Edwin Fulcher and Keith Newman, filed on Jul. 21, 1992, and assigned to LSI Logic Corporation, the disclosure of which is incorporated by reference herein for all purposes.
As used herein, the term "semiconductor device assembly" refers to a semiconductor die, one or more printed wiring boards, and the associated structure with which the semiconductor die is connected, including connections to a socket or system printed circuit board, and internal connections such as bond wiring.
Connections Between Semiconductor Die and Bond Fingers
Semiconductor device assemblies include bond fingers that are typically arranged in a rectangular array surrounding a semiconductor die. Connections to the semiconductor die are ordinarily achieved by bond wires that are adapted to connect the bond pads of a semiconductor die to surrounding bond fingers. The number and arrangement of bond fingers thus determines the size of the rectangular array that is necessary to expose each bond finger for connection thereto. The semiconductor die must fit squarely within the rectangular array formed by the bond fingers in order to minimize the bond wire lengths between the semiconductor die and bond fingers. Thus, the greater the number of bond fingers in a rectangular array, the larger must be the size of the semiconductor die.
Currently known semiconductor device assemblies rely upon bond fingers to satisfy all connections to a semiconductor die. Currently known semiconductor device assemblies utilize bond fingers to provide all connections between a semiconductor and external circuitry. Such connections include power supply connections, such as ground and power source, as well as signal connections. Power supply connections ordinarily utilize approximately 10% of the bond fingers. Thus, the use of bond fingers for power supply connections results in a significant increase in the size of the rectangular array of bond fingers. This requires a semiconductor die of an increased size.
FIGS. 1 and 2 illustrate a prior art printed wiring board 100. Referring to FIG. 1, the top conductive surface 101 of printed wiring board 100 is illustrated. Top conductive surface 101 includes a set of leads as generally indicated by reference numerals 102. Connected to leads 102 are vias (also referred to as "plated through-holes") as generally indicated by reference numerals 104. Vias 104 connect leads 102 to external connection means such as solder balls (not illustrated). On the other end of leads 102 are signal bond fingers which are generally indicated by reference numerals 106. Signal bond fingers 106 are electrically connected to respective bond pads of a semiconductor die (not illustrated) by bond wires for the transmission of signals therebetween. Thus, signals to and from a semiconductor die connect through bond wires through signal bond fingers 106, through leads 102, through vias 104, to external system circuitry.
Top conductive surface 101 provides for power to be supplied to a semiconductor die by connection with bond fingers that are generally indicated by reference numeral 108. Power bond fingers 108 are interleaved with signal bond fingers 106. Power bond fingers 108 are connected to vias 116. Vias 116 provide for connections to a power supply. Thus, power from a power source is provided to a semiconductor die through an external connection means, through vias 116, through power bond fingers 108 through bond wiring, and onto a semiconductor die (by means of bond pads).
A semiconductor die must also be supplied with connections. Top conductive surface 101 includes a ground plane as indicated by reference numeral 110. Ground plane 110 includes ground bond fingers 114 which are interleaved in the same rectangular array as signal bond fingers 106 and power bond fingers 108. Ground plane 110 is connected to ground vias 112 which, in turn, connect ground plane 110 to external ground. Thus, ground is provided to a semiconductor die through an external connection means, through vias 112, through ground bond fingers 114 through bond wiring, and onto a semiconductor die (by means of bond pads).
Vias 112 and 116 connect top conductive surface 101 of printed wiring board 100 to a bottom conductive surface, as illustrated in FIG. 2. External connection means, such as solder balls (of BGA type packages), are connected to respective contact pads. Contact pads are generally indicated by reference numerals 206. Some of the contact pads correspond to a conductive pattern. Bottom conductive surface 201 contains several conductive patterns, namely, ground pattern 202, as well as power patterns 204a-d. Ground pattern 202 is connected to ground plane 110 (and ground bond fingers 114) through vias 112. Contact pads 206g are connected to ground pattern 202 so that solder balls which are connected to contact pads 206g will pass a ground. Similarly, power patterns 204a-d are connected to power bond fingers 108 through vias 116. Contact pads 206p are connected to power patterns 204a-d so that solder balls which are connected to contact pads 206p will pass power between a semiconductor die and external circuitry. Bottom conductive surface 201 also includes contact pads 206s. Contact pads 206s are electrically connected to vias 104 by conductive leads (not illustrated). Vias 104 further connect to signal bond fingers 106 so that solder balls that are connected to contact pads 206s will pass signals between a semiconductor die and external circuitry.
By interleaving signal bond fingers 106 with power bond fingers 108 and ground bond fingers 114, the rectangular array formed by such bond fingers is significantly expanded. This has the undesirable effect of requiring an increase in the size of the semiconductor die which must be in close proximate alignment with signal bond fingers 106, power bond fingers 108 and ground bond fingers 114 in order to minimize the bond wire lengths.
In sum, the prior art of which the applicant is aware fails to disclose the ability to provide for power supply connections, such as a ground and power source other than through the utilization of bond fingers or contacts that are aligned therewith. In doing so, the size of the array formed by the bond fingers of a semiconductor device assembly is significantly increased. A semiconductor die, which is employed in conjunction with such a semiconductor device assembly, must therefore be of a size larger than necessary to conform to the array of bond fingers. What is needed is a semiconductor device assembly having improved semiconductor connections that employ a minimum number of bond fingers.